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.gitignore
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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add_sub.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
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adffs.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
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bug1597.ys
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Import tests from #1628
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2020-01-27 13:56:16 -08:00 |
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bug1598.ys
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Add #1598 testcase
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2019-12-27 16:44:57 -08:00 |
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bug1626.ys
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Add #1626 testcase
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2020-01-12 15:21:26 -08:00 |
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bug1644.il.gz
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Add #1644 testcase
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2020-01-17 15:57:52 -08:00 |
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bug1644.ys
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Add #1644 testcase
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2020-01-17 15:57:52 -08:00 |
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counter.ys
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Call equiv_opt with -multiclock and -assert
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2019-12-31 18:39:32 -08:00 |
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dffs.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
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dpram.v
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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dpram.ys
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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fsm.ys
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Fixed tests
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2019-11-11 15:41:33 +01:00 |
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ice40_dsp.ys
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test: ice40_dsp test to read +/ice40/cells_sim.v for default params
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2020-04-22 16:35:35 -07:00 |
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ice40_opt.ys
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Import tests from #1628
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2020-01-27 13:56:16 -08:00 |
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ice40_wrapcarry.ys
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Change attribute search value to specify precise location instead of simple line number.
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2020-02-24 02:41:08 +00:00 |
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latches.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
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logic.ys
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2019-10-18 12:19:59 +02:00 |
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macc.v
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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macc.ys
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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memories.ys
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tests: remove write_ilang
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2020-04-20 15:42:29 -07:00 |
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mul.ys
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Fix warnings
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2019-12-31 18:40:11 -08:00 |
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mux.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
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rom.v
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Revert insertion of 'reg', leave note behind
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2020-01-01 09:05:46 -08:00 |
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rom.ys
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Moved all tests in arch sub directory
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2019-10-18 11:06:12 +02:00 |
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run-test.sh
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Fix path to yosys
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2019-10-18 11:12:03 +02:00 |
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shifter.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
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tribuf.ys
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Share common tests
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2019-10-18 12:19:59 +02:00 |
