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22 lines
564 B
Verilog
22 lines
564 B
Verilog
(* blackbox *)
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module bb(output y);
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endmodule
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// all instances of `m` tie together a[1], a[2]
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// this can be used to conclude y[0]=0
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module m(input [3:0] a, output [1:0] y, output x);
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assign y[0] = a[1] != a[2];
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assign x = a[0] ^ a[3];
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(* should_get_optimized_out *)
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bb bb1(.y(y[1]));
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endmodule
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module top(input j, output z, output [2:0] x);
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wire [1:0] y1;
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wire [1:0] y2;
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wire [1:0] y3;
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m inst1(.a(0), .y(y1), .x(x[0]));
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m inst2(.a(15), .y(y2), .x(x[1]));
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m inst3(.a({1'b1, j, j, 1'b0}), .y(y3), .x(x[2]));
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assign z = (&y1) ^ (&y2) ^ (&y3);
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endmodule
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