mirror of
https://github.com/YosysHQ/yosys
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113 lines
3.2 KiB
Text
113 lines
3.2 KiB
Text
### Always-active SRST removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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(* init=12'h555 *)
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output [11:0] Q;
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input SRST;
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input EN;
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b1), .D(D), .Q(Q[1:0]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[3:2]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b0), .EN(EN), .D(D), .Q(Q[5:4]));
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff3 (.CLK(CLK), .SRST(1'bx), .D(D), .Q(Q[7:6]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff4 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[9:8]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff5 (.CLK(CLK), .SRST(1'bx), .EN(EN), .D(D), .Q(Q[11:10]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-count 0 t:$sdff
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select -assert-count 0 t:$sdffe
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select -assert-count 0 t:$sdffce
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select -assert-count 4 t:$dff
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select -assert-count 2 t:$dffe
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design -load orig
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 1 t:$sdff
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select -assert-count 1 t:$sdffe
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select -assert-count 1 t:$sdffce
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select -assert-count 2 t:$dff
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select -assert-count 1 t:$dffe
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:$_SDFF_???_
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select -assert-none t:$_SDFFE_????_
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select -assert-none t:$_SDFFCE_????_
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select -assert-count 8 t:$_DFF_?_
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select -assert-count 4 t:$_DFFE_??_
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff -keepdc
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design -load postopt
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select -assert-count 2 t:$_SDFF_???_
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select -assert-count 2 t:$_SDFFE_????_
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select -assert-count 2 t:$_SDFFCE_????_
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select -assert-count 4 t:$_DFF_?_
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select -assert-count 2 t:$_DFFE_??_
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design -reset
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### Never-active SRST removal.
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read_verilog -icells <<EOT
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module top(...);
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input CLK;
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input [1:0] D;
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output [5:0] Q;
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input SRST;
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input EN;
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$sdff #(.CLK_POLARITY(1'b1), .SRST_POLARITY(1'b1), .SRST_VALUE(2'h2), .WIDTH(2)) ff0 (.CLK(CLK), .SRST(1'b0), .D(D), .Q(Q[1:0]));
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$sdffe #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff1 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[3:2]));
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$sdffce #(.CLK_POLARITY(1'b1), .EN_POLARITY(1'b1), .SRST_POLARITY(1'b0), .SRST_VALUE(2'h2), .WIDTH(2)) ff2 (.CLK(CLK), .SRST(1'b1), .EN(EN), .D(D), .Q(Q[5:4]));
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endmodule
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EOT
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design -save orig
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:$sdff
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select -assert-none t:$sdffe
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select -assert-none t:$sdffce
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select -assert-count 1 t:$dff
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select -assert-count 2 t:$dffe
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design -load orig
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simplemap
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equiv_opt -undef -assert -multiclock opt_dff
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design -load postopt
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select -assert-none t:$_SDFF_???_
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select -assert-none t:$_SDFFE_????_
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select -assert-none t:$_SDFFCE_????_
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select -assert-count 2 t:$_DFF_P_
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select -assert-count 4 t:$_DFFE_PP_
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design -reset
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