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19 lines
451 B
Verilog
19 lines
451 B
Verilog
module demo1(input clk, input addtwo, output iseven);
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reg [3:0] cnt;
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wire [3:0] next_cnt;
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inc inc_inst (addtwo, iseven, cnt, next_cnt);
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always @(posedge clk)
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cnt = (iseven ? cnt == 10 : cnt == 11) ? 0 : next_cnt;
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`ifdef FORMAL
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assert property (cnt != 15);
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initial assume (!cnt[2]);
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`endif
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endmodule
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module inc(input addtwo, output iseven, input [3:0] a, output [3:0] y);
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assign iseven = !a[0];
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assign y = a + (addtwo ? 2 : 1);
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endmodule
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