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22 lines
331 B
Systemverilog
22 lines
331 B
Systemverilog
module top (
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input clk,
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input [2:0] a,
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input [2:0] b
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);
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default clocking @(posedge clk); endclocking
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assert property (
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$changed(a)
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);
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assert property (
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$changed(b) == ($changed(b[0]) || $changed(b[1]) || $changed(b[2]))
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);
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`ifndef FAIL
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assume property (
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a !== 'x ##1 $changed(a)
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);
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`endif
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endmodule
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