Jannis Harder a855d62b42 verific: Improve logic generated for SVA value change expressions ... The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation		2022-05-09 15:04:01 +02:00
..
aiger	switch argument order to work with macOS getopt	2020-09-23 12:48:26 +02:00
arch	intel_alm: M10K write-enable is negative-true	2022-03-09 20:18:06 +00:00
asicworld	Fix FIRRTL to Verilog process instance subfield assignment.	2019-02-25 16:18:13 -08:00
bind	Add support for parsing the SystemVerilog 'bind' construct	2021-07-16 09:31:39 -04:00
blif	tests/blif: Add missing gitignore	2021-05-20 12:49:51 +02:00
bram	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
errors	Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,	2018-10-25 02:37:56 +03:00
fsm	tests: fsm to use a randomly-generated seed	2020-04-24 14:31:33 -07:00
hana	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
liberty	dfflibmap: Refactor to use dfflegalize internally.	2020-07-09 18:51:03 +02:00
lut	Forgot to commit	2019-07-16 12:44:26 -07:00
memfile	Added 'set -e' into tests/memfile/run-test.sh	2020-02-06 10:45:40 -03:00
memories	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
opt	opt_merge: Add -keepdc option required for formal verification	2022-04-01 21:03:20 +02:00
opt_share	tests: Parallelize	2020-09-21 15:07:02 +02:00
proc	proc_prune: Make assign removal and promotion per-bit, remember promoted bits.	2021-08-14 15:26:11 +02:00
realmath	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
rpc	rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors	2020-03-06 15:29:01 +01:00
sat	Proper example code	2022-03-14 15:39:11 +01:00
select	Merge pull request #1949 from YosysHQ/eddie/select_blackbox	2020-04-22 15:35:05 -07:00
share	Add optional SEED=n command line option to Makefile, and -S n command line option to test scripts, for deterministic regression tests.	2016-09-22 11:49:29 -06:00
sim	test dlatchsr and adlatch	2022-02-16 13:58:51 +01:00
simple	Fix valgrind tests when using verific	2022-03-30 17:25:53 +02:00
simple_abc9	abc9: fix SCC issues (#2694)	2021-03-29 22:01:57 -07:00
smv	Progress in SMV back-end	2015-06-19 14:08:46 +02:00
sva	verific: Improve logic generated for SVA value change expressions	2022-05-09 15:04:01 +02:00
svinterfaces	Add a test for interfaces on modules loaded on-demand	2021-07-14 22:54:50 -04:00
svtypes	sv: improve support for wire and var with user-defined types	2021-08-12 22:41:41 -06:00
techmap	opt_mem: Remove constant-value bit lanes.	2022-05-07 23:13:16 +02:00
tools	Fixes in vcdcd.pl for newer Perl versions	2021-10-19 10:56:43 +02:00
unit	Build hotfix in tests/unit/Makefile	2016-12-11 10:58:49 +01:00
various	fix handling of escaped chars in json backend and frontend	2022-02-18 17:13:09 +01:00
verilog	sv: fix always_comb auto nosync for nested and function blocks	2022-04-05 14:43:48 -06:00
vloghtb	Use HTTPS for website links, gatecat email	2021-06-09 12:16:56 +02:00
gen-tests-makefile.sh	tests: Parallelize	2020-09-21 15:07:02 +02:00