mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
8 lines
132 B
Systemverilog
8 lines
132 B
Systemverilog
module top;
|
|
rand const reg rx;
|
|
const reg ry;
|
|
rand reg rz;
|
|
rand const integer ix;
|
|
const integer iy;
|
|
rand integer iz;
|
|
endmodule
|