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44 lines
742 B
Verilog
44 lines
742 B
Verilog
module pmux2shiftx_test (
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input [2:0] S1,
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input [5:0] S2,
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input [1:0] S3,
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input [9:0] A, B, C, D, D, E, F, G, H,
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input [9:0] I, J, K, L, M, N, O, P, Q,
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output reg [9:0] X
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);
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always @* begin
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case (S1)
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3'd 0: X = A;
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3'd 1: X = B;
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3'd 2: X = C;
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3'd 3: X = D;
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3'd 4: X = E;
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3'd 5: X = F;
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3'd 6: X = G;
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3'd 7: X = H;
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endcase
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case (S2)
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6'd 45: X = I;
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6'd 47: X = J;
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6'd 49: X = K;
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6'd 55: X = L;
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6'd 57: X = M;
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6'd 59: X = N;
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endcase
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case (S3)
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2'd 1: X = O;
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2'd 2: X = P;
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2'd 3: X = Q;
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endcase
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end
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endmodule
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module issue01135(input [7:0] i, output reg o);
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always @*
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case (i[6:3])
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4: o <= i[0];
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3: o <= i[2];
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7: o <= i[3];
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default: o <= 1'b0;
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endcase
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endmodule
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