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https://github.com/YosysHQ/yosys
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35 lines
699 B
Text
35 lines
699 B
Text
design -reset
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read_verilog <<EOT
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module top(input g, rn, d, output reg q);
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always @* if (~rn) q <= 0; else if (g) q <= d;
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endmodule
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EOT
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hierarchy -top top
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proc
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select -assert-count 1 t:$dlatch
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logger -expect warning "is a latch of type" 1
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check -nolatches
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logger -check-expected
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design -reset
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read_verilog <<EOT
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module top(input g, d, output reg q);
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always @* q = g ? d : 1'b0;
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endmodule
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EOT
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hierarchy -top top
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proc
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check -nolatches -assert
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design -reset
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read_verilog <<EOT
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module top(input g, d, output reg q, output y);
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always @* if (g) q = d;
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wire u;
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assign y = u;
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endmodule
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EOT
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hierarchy -top top
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proc
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logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
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check -latchonly -assert
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