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20 lines
394 B
Verilog
20 lines
394 B
Verilog
module top (
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input clock,
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input [31:0] dinA, dinB,
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input [2:0] opcode,
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output reg [31:0] dout
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);
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always @(posedge clock) begin
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case (opcode)
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0: dout <= dinA + dinB;
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1: dout <= dinA - dinB;
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2: dout <= dinA >> dinB;
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3: dout <= $signed(dinA) >>> dinB;
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4: dout <= dinA << dinB;
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5: dout <= dinA & dinB;
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6: dout <= dinA | dinB;
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7: dout <= dinA ^ dinB;
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endcase
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end
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endmodule
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