mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-24 17:45:33 +00:00
9 lines
404 B
Text
9 lines
404 B
Text
read_verilog div_mod.v
|
|
hierarchy -top top
|
|
flatten
|
|
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
select -assert-count 62 t:SB_LUT4
|
|
select -assert-count 41 t:SB_CARRY
|
|
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
|