mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-28 11:25:53 +00:00
5 lines
137 B
Verilog
5 lines
137 B
Verilog
// ---------------------------------------
|
|
|
|
(* abc_box_id=2 *)
|
|
module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
|
|
endmodule
|