mirror of
https://github.com/YosysHQ/yosys
synced 2026-03-23 04:49:15 +00:00
366 lines
10 KiB
C++
366 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct TribufConfig {
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bool merge_mode;
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bool logic_mode;
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bool formal_mode;
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bool nested_mode;
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TribufConfig() {
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merge_mode = false;
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logic_mode = false;
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formal_mode = false;
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nested_mode = false;
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}
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};
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struct TribufWorker {
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Module *module;
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SigMap sigmap;
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const TribufConfig &config;
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TribufWorker(Module *module, const TribufConfig &config) : module(module), sigmap(module), config(config)
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{
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}
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static bool is_all_z(SigSpec sig)
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{
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for (auto bit : sig)
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if (bit != State::Sz)
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return false;
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return true;
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}
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private:
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struct TribufSelPart {
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SigSpec sig;
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bool inv;
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TribufSelPart(const SigSpec &sig, bool inv) : sig(sig), inv(inv)
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{
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}
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};
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typedef std::vector<TribufSelPart> TribufSel;
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static bool collect_tribuf_cell(Cell *cell, TribufSel &sel, const dict<SigSpec, vector<Cell*>> &muxes)
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{
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if (cell->type.in(ID($tribuf), ID($_TBUF_)))
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{
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sel.emplace_back(cell->getPort(ID::EN), /*inv*/ true);
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return true;
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}
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log_assert(cell->type.in(ID($mux), ID($_MUX_)));
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const SigSpec &s_sig = cell->getPort(ID::S);
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const SigSpec &a_sig = cell->getPort(ID::A);
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const SigSpec &b_sig = cell->getPort(ID::B);
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vector<Cell*> cells = muxes.at(a_sig, {});
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// We specifically ignore cases when there are multiple
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// driving multiplexers.
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Cell *next_cell = (cells.size() == 1) ? cells.front() : nullptr;
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if ((next_cell && collect_tribuf_cell(next_cell, sel, muxes)) || is_all_z(a_sig))
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{
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sel.emplace_back(s_sig, /*inv*/ true);
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return true;
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}
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cells = muxes.at(b_sig, {});
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next_cell = (cells.size() == 1) ? cells.front() : nullptr;
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if ((next_cell && collect_tribuf_cell(next_cell, sel, muxes)) || is_all_z(b_sig))
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{
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sel.emplace_back(s_sig, /*inv*/ false);
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return true;
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}
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return false;
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}
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static SigSpec construct_new_sel(Module *module, const TribufSel &new_sel)
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{
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size_t count = new_sel.size();
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log_assert(count > 0);
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Wire *res_wire = nullptr;
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Cell *res_cell = nullptr;
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SigSpec result = new_sel[0].sig;
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if (new_sel[0].inv)
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{
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res_wire = module->addWire(NEW_ID, new_sel[0].sig.size());
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res_cell = module->addNot(NEW_ID, result, res_wire);
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result = res_cell->getPort(ID::Y);
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}
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for (size_t i = 1; i < count; ++i)
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{
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const TribufSelPart &sel_part = new_sel[i];
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SigSpec curr_sig = sel_part.sig;
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if (sel_part.inv)
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{
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res_wire = module->addWire(NEW_ID, sel_part.sig.size());
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res_cell = module->addNot(NEW_ID, sel_part.sig, res_wire);
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curr_sig = res_cell->getPort(ID::Y);
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}
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res_wire = module->addWire(NEW_ID, std::max(curr_sig.size(), result.size()));
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res_cell = module->addAnd(NEW_ID, result, curr_sig, res_wire);
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result = res_cell->getPort(ID::Y);
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}
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return result;
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}
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static void nested_mux_to_tribuf(Module *module, Cell *cell, dict<SigSpec, vector<Cell*>> &tribufs, const dict<SigSpec, vector<Cell*>> &muxes)
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{
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TribufSel new_sel;
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// Collect all selector parts by traversing multiplexers recursively.
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if (!collect_tribuf_cell(cell, new_sel, muxes))
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return;
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// Construct a conjunction of all selectors leading to Z-vector.
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SigSpec new_sel_sig = construct_new_sel(module, new_sel);
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SigSpec old_sig = cell->getPort(ID::Y);
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// Create a new wire to rebind old multiplexer to.
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Wire *mux_wire = module->addWire(NEW_ID, old_sig.size());
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cell->setPort(ID::Y, mux_wire);
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// Create an inverse of the conjunction to create the new tri-state cell.
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Wire *not_wire = module->addWire(NEW_ID, new_sel_sig.size());
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module->addNot(NEW_ID, new_sel_sig, not_wire);
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Cell *tribuf_cell = module->addTribuf(NEW_ID, mux_wire, not_wire, old_sig);
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tribufs[old_sig].push_back(tribuf_cell);
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}
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public:
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void run()
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{
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dict<SigSpec, vector<Cell*>> tribuf_cells;
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dict<SigSpec, vector<Cell*>> y_port_to_mux;
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pool<SigBit> output_bits;
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if (config.logic_mode || config.formal_mode)
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for (auto wire : module->wires())
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if (wire->port_output)
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for (auto bit : sigmap(wire))
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output_bits.insert(bit);
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for (auto cell : module->selected_cells())
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{
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if (config.nested_mode && cell->type.in(ID($tribuf), ID($_TBUF_), ID($mux), ID($_MUX_)))
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y_port_to_mux[sigmap(cell->getPort(ID::Y))].push_back(cell);
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if (cell->type == ID($tribuf))
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tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
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if (cell->type == ID($_TBUF_))
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tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
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if (cell->type.in(ID($mux), ID($_MUX_)))
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{
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IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E;
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IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
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bool a_all_z = is_all_z(cell->getPort(ID::A));
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bool b_all_z = is_all_z(cell->getPort(ID::B));
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if (a_all_z && b_all_z) {
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module->remove(cell);
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continue;
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}
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if (a_all_z) {
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cell->setPort(ID::A, cell->getPort(ID::B));
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cell->setPort(en_port, cell->getPort(ID::S));
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cell->unsetPort(ID::B);
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cell->unsetPort(ID::S);
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cell->type = tri_type;
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tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
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module->design->scratchpad_set_bool("tribuf.added_something", true);
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continue;
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}
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if (b_all_z) {
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cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
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cell->unsetPort(ID::B);
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cell->unsetPort(ID::S);
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cell->type = tri_type;
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tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
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module->design->scratchpad_set_bool("tribuf.added_something", true);
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continue;
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}
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}
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}
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if (config.nested_mode)
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{
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for (auto &[y_sig, muxes]: y_port_to_mux)
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{
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for (Cell *cell: muxes)
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{
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// Tri-state cells are handled later, so at this point
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// we need to process only "true" multiplexers.
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if (cell->type.in(ID($mux), ID($_MUX_)))
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nested_mux_to_tribuf(module, cell, tribuf_cells, y_port_to_mux);
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}
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}
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}
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if (config.merge_mode || config.logic_mode || config.formal_mode)
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{
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for (auto &it : tribuf_cells)
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{
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bool no_tribuf = false;
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if (config.logic_mode && !config.formal_mode) {
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no_tribuf = true;
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for (auto bit : it.first)
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if (output_bits.count(bit))
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no_tribuf = false;
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}
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if (config.formal_mode)
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no_tribuf = true;
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if (GetSize(it.second) <= 1 && !no_tribuf)
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continue;
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if (config.formal_mode && GetSize(it.second) >= 2) {
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for (auto cell : it.second) {
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SigSpec others_s;
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for (auto other_cell : it.second) {
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if (other_cell == cell)
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continue;
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else if (other_cell->type == ID($tribuf))
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others_s.append(other_cell->getPort(ID::EN));
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else
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others_s.append(other_cell->getPort(ID::E));
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}
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auto cell_s = cell->type == ID($tribuf) ? cell->getPort(ID::EN) : cell->getPort(ID::E);
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auto other_s = module->ReduceOr(NEW_ID, others_s);
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auto conflict = module->And(NEW_ID, cell_s, other_s);
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std::string name = stringf("$tribuf_conflict$%s", log_id(cell->name));
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auto assert_cell = module->addAssert(name, module->Not(NEW_ID, conflict), SigSpec(true));
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assert_cell->set_src_attribute(cell->get_src_attribute());
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assert_cell->set_bool_attribute(ID::keep);
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module->design->scratchpad_set_bool("tribuf.added_something", true);
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}
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}
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SigSpec pmux_b, pmux_s;
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for (auto cell : it.second) {
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if (cell->type == ID($tribuf))
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pmux_s.append(cell->getPort(ID::EN));
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else
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pmux_s.append(cell->getPort(ID::E));
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pmux_b.append(cell->getPort(ID::A));
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module->remove(cell);
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}
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SigSpec muxout = GetSize(pmux_s) > 1 ? module->Pmux(NEW_ID, SigSpec(State::Sx, GetSize(it.first)), pmux_b, pmux_s) : pmux_b;
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if (no_tribuf)
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module->connect(it.first, muxout);
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else {
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module->addTribuf(NEW_ID, muxout, module->ReduceOr(NEW_ID, pmux_s), it.first);
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module->design->scratchpad_set_bool("tribuf.added_something", true);
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}
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}
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}
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}
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};
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struct TribufPass : public Pass {
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TribufPass() : Pass("tribuf", "infer tri-state buffers") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" tribuf [options] [selection]\n");
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log("\n");
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log("This pass transforms $mux cells with 'z' inputs to tristate buffers.\n");
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log("\n");
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log(" -merge\n");
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log(" merge multiple tri-state buffers driving the same net\n");
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log(" into a single buffer.\n");
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log("\n");
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log(" -logic\n");
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log(" convert tri-state buffers that do not drive output ports\n");
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log(" to non-tristate logic. this option implies -merge.\n");
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log("\n");
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log(" -formal\n");
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log(" convert all tri-state buffers to non-tristate logic and\n");
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log(" add a formal assertion that no two buffers are driving the\n");
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log(" same net simultaneously. this option implies -merge.\n");
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log("\n");
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log(" -nested\n");
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log(" convert multiplexers using tri-state cells to tri-state cells\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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TribufConfig config;
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log_header(design, "Executing TRIBUF pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-merge") {
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config.merge_mode = true;
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continue;
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}
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if (args[argidx] == "-logic") {
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config.logic_mode = true;
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continue;
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}
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if (args[argidx] == "-formal") {
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config.formal_mode = true;
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continue;
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}
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if (args[argidx] == "-nested") {
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config.nested_mode = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules()) {
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TribufWorker worker(module, config);
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worker.run();
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}
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}
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} TribufPass;
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PRIVATE_NAMESPACE_END
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