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baa3659ea5
Parallel connections do not allow matching different bit widths. A full connection has to be used instead. Allows iverilog to parse the simulation library with hardware path delays enabled. |
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| .. | ||
| tests | ||
| abc9_model.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| dsp_map.v | ||
| ff_map.v | ||
| ice40_braminit.cc | ||
| ice40_opt.cc | ||
| latches_map.v | ||
| Makefile.inc | ||
| spram.txt | ||
| spram_map.v | ||
| synth_ice40.cc | ||