yosys/tests/verilog/gen_block_end_label_only.ys at a6b3113a66f13e439eea357f472d868c4a98ba78 - mirrors/yosys - Libre-Chip.org

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Zachary Snow f2c2d73f36 sv: fix up end label checking

- disallow [gen]blocks with an end label but not begin label
- check validity of module end label
- fix memory leak of package name and end label
- fix memory leak of module end label

2021-06-16 21:48:05 -04:00

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 logger -expect error "Begin label missing where end label \(incorrect_name\) was given\." 1
 read_verilog -sv <<EOF
 module top;
 if (1)
     begin
         initial $display("HI");
     end : incorrect_name
 endmodule
 EOF