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4edb1a1921
- Add support for assignments within expressions, e.g., `x[y++] = z;` or `x = (y *= 2) - 1;`. The logic is handled entirely within the parser by injecting statements into the current procedural block. - Add support for pre-increment/decrement statements, which are behaviorally equivalent to post-increment/decrement statements. - Fix non-standard attribute position used for post-increment/decrement statements.
15 lines
238 B
Text
15 lines
238 B
Text
read_verilog -sv <<EOF
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module top;
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integer x, y;
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initial y = (x += 1);
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endmodule
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EOF
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design -reset
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logger -expect error "syntax error, unexpected TOK_ID" 1
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read_verilog <<EOF
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module top;
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integer x, y;
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initial y = (x += 1);
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endmodule
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EOF
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