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yosys/tests/errors/syntax_err07.v
Miodrag Milanovic 48a3dcc02a End of file fix
2026-06-23 07:23:41 +02:00

5 lines
64 B
Verilog

module a;
wire [5:0]x;
wire [3:0]y;
assign y = (4)55;
endmodule