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yosys/frontends
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Jannis Harder 79e05a195d verilog: Bufnorm cell backend and frontend support 
This makes the Verilog backend handle the $connect and $input_port
cells. This represents the undirected $connect cell using the `tran`
primitive, so we also extend the frontend to support this.
2025-09-17 14:01:09 +02:00
..
aiger Update frontends to avoid bits() 2025-09-16 03:17:23 +00:00
aiger2 Remove .c_str() calls from log()/log_error() 2025-09-11 20:59:37 +00:00
ast verilog: Bufnorm cell backend and frontend support 2025-09-17 14:01:09 +02:00
blif Update frontends to avoid bits() 2025-09-16 03:17:23 +00:00
json Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
liberty Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
rpc Remove .c_str() calls from parameters to log_header() 2025-09-16 23:00:42 +00:00
rtlil Use fast path for 32-bit Const integer constructor in more places 2025-09-16 03:17:24 +00:00
verific Remove .c_str() calls from parameters to log_warning()/log_warning_noprefix() 2025-09-16 23:02:16 +00:00
verilog verilog: Bufnorm cell backend and frontend support 2025-09-17 14:01:09 +02:00