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80 lines
1.6 KiB
Text
80 lines
1.6 KiB
Text
read_verilog << EOT
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module top(input wire [14:0] a, output wire [18:0] b);
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assign b = a*$unsigned(5'b01111);
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endmodule
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EOT
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prep
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ice40_dsp
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read_verilog << EOT
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module ref(a, b);
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wire _0_;
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wire _1_;
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wire _2_;
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wire [12:0] _3_;
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(* src = "<<EOT:1.30-1.31" *)
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input [14:0] a;
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wire [14:0] a;
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(* src = "<<EOT:1.52-1.53" *)
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output [18:0] b;
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wire [18:0] b;
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SB_MAC16 #(
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.A_REG(1'h0),
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.A_SIGNED(32'd0),
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.BOTADDSUB_CARRYSELECT(2'h0),
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.BOTADDSUB_LOWERINPUT(2'h2),
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.BOTADDSUB_UPPERINPUT(1'h1),
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.BOTOUTPUT_SELECT(2'h3),
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.BOT_8x8_MULT_REG(1'h0),
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.B_REG(1'h0),
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.B_SIGNED(32'd0),
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.C_REG(1'h0),
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.D_REG(1'h0),
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.MODE_8x8(1'h0),
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.NEG_TRIGGER(1'h0),
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.PIPELINE_16x16_MULT_REG1(1'h0),
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.PIPELINE_16x16_MULT_REG2(1'h0),
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.TOPADDSUB_CARRYSELECT(2'h3),
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.TOPADDSUB_LOWERINPUT(2'h2),
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.TOPADDSUB_UPPERINPUT(1'h1),
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.TOPOUTPUT_SELECT(2'h3),
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.TOP_8x8_MULT_REG(1'h0)
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) _4_ (
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.A({ 1'h0, a }),
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.ACCUMCI(1'hx),
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.ACCUMCO(_1_),
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.ADDSUBBOT(1'h0),
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.ADDSUBTOP(1'h0),
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.AHOLD(1'h0),
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.B(16'b1111),
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.BHOLD(1'h0),
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.C(16'h0000),
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.CE(1'h0),
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.CHOLD(1'h0),
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.CI(1'hx),
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.CLK(1'h0),
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.CO(_2_),
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.D(16'h0000),
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.DHOLD(1'h0),
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.IRSTBOT(1'h0),
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.IRSTTOP(1'h0),
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.O({ _3_, b }),
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.OHOLDBOT(1'h0),
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.OHOLDTOP(1'h0),
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.OLOADBOT(1'h0),
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.OLOADTOP(1'h0),
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.ORSTBOT(1'h0),
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.ORSTTOP(1'h0),
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.SIGNEXTIN(1'hx),
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.SIGNEXTOUT(_0_)
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);
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endmodule
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EOT
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techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
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equiv_make top ref equiv
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select -assert-any -module equiv t:$equiv
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equiv_induct
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equiv_status -assert
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