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https://github.com/YosysHQ/yosys
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39 lines
1.2 KiB
C++
39 lines
1.2 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* ---
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*
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* A simple and straightforward Verilog backend.
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*
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*/
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#ifndef VERILOG_BACKEND_H
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#define VERILOG_BACKEND_H
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#include <string>
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YOSYS_NAMESPACE_BEGIN
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namespace VERILOG_BACKEND {
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const pool<string> verilog_keywords();
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bool char_is_verilog_escaped(char c);
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bool id_is_verilog_escaped(const std::string &str);
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}; /* namespace VERILOG_BACKEND */
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YOSYS_NAMESPACE_END
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#endif /* VERILOG_BACKEND_H */
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