mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-30 19:22:31 +00:00
210 lines
6.9 KiB
C++
210 lines
6.9 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Marcelina Kościelnicka <mwk@0x04.net>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/celltypes.h"
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#include "kernel/mem.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct CleanZeroWidthPass : public Pass {
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CleanZeroWidthPass() : Pass("clean_zerowidth", "clean zero-width connections from the design") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clean_zerowidth [selection]\n");
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log("\n");
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log("Fixes the selected cells and processes to contain no zero-width connections.\n");
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log("Depending on the cell type, this may be implemented by removing the connection,\n");
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log("widening it to 1-bit, or removing the cell altogether.\n");
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log("\n");
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}
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void clean_case(RTLIL::CaseRule *cs)
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{
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std::vector<SigSig> new_actions;
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for (auto &action : cs->actions)
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if (GetSize(action.first) != 0)
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new_actions.push_back(action);
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std::swap(new_actions, cs->actions);
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for (auto sw : cs->switches)
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for (auto scs : sw->cases)
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clean_case(scs);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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CellTypes ct;
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ct.setup();
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for (auto module : design->selected_modules())
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{
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for (auto cell : module->selected_cells())
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{
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if (!ct.cell_known(cell->type)) {
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// User-defined cell: just prune zero-width connections.
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for (auto it: cell->connections()) {
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if (GetSize(it.second) == 0) {
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cell->unsetPort(it.first);
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}
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}
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} else if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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// Coarse FF cells: remove if WIDTH == 0 (no outputs).
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// This will also trigger on fine cells, so use the Q port
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// width instead of actual WIDTH parameter.
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if (GetSize(cell->getPort(ID::Q)) == 0) {
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module->remove(cell);
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}
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} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
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// Remove altogether if WIDTH is 0, replace with
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// a connection if S_WIDTH is 0.
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if (cell->getParam(ID::WIDTH).as_int() == 0) {
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module->remove(cell);
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}
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if (cell->getParam(ID::S_WIDTH).as_int() == 0) {
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->remove(cell);
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}
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} else if (cell->type == ID($concat)) {
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// If a concat has a zero-width input: replace with direct
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// connection to the other input.
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if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::B));
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module->remove(cell);
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} else if (cell->getParam(ID::B_WIDTH).as_int() == 0) {
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module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
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module->remove(cell);
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}
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} else if (cell->type == ID($fsm)) {
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// TODO: not supported
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} else if (cell->is_mem_cell()) {
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// Skip — will be handled below.
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} else if (cell->type == ID($lut)) {
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// Zero-width LUT is just a const driver.
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if (cell->getParam(ID::WIDTH).as_int() == 0) {
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module->connect(cell->getPort(ID::Y), cell->getParam(ID::LUT)[0]);
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module->remove(cell);
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}
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} else if (cell->type == ID($sop)) {
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// Zero-width SOP is just a const driver.
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if (cell->getParam(ID::WIDTH).as_int() == 0) {
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// The value is 1 iff DEPTH is non-0.
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bool val = cell->getParam(ID::DEPTH).as_int() != 0;
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module->connect(cell->getPort(ID::Y), val);
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module->remove(cell);
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}
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} else if (cell->hasParam(ID::WIDTH)) {
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// For cells with WIDTH parameter: remove if zero.
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if (cell->getParam(ID::WIDTH).as_int() == 0) {
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module->remove(cell);
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}
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} else if (cell->hasParam(ID::Y_WIDTH)) {
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// For most operators: remove if Y width is 0, expand
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// A and B to 1-bit if their width is 0.
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if (cell->getParam(ID::Y_WIDTH).as_int() == 0) {
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module->remove(cell);
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} else if (cell->type.in(ID($macc), ID($macc_v2))) {
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// TODO: fixing zero-width A and B not supported.
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} else {
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if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
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cell->setPort(ID::A, State::S0);
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cell->setParam(ID::A_WIDTH, 1);
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}
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if (cell->hasParam(ID::B_WIDTH) && cell->getParam(ID::B_WIDTH).as_int() == 0) {
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cell->setPort(ID::B, State::S0);
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cell->setParam(ID::B_WIDTH, 1);
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}
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}
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}
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}
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// NOTE: Zero-width switch signals are left alone for processes, as there
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// is no simple way of cleaning them up.
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for (auto &it: module->processes) {
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if (!design->selected(module, it.second))
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continue;
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clean_case(&it.second->root_case);
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for (auto sync : it.second->syncs) {
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std::vector<int> swizzle;
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std::vector<RTLIL::MemWriteAction> new_memwr_actions;
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for (int i = 0; i < GetSize(sync->mem_write_actions); i++) {
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auto &memwr = sync->mem_write_actions[i];
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if (GetSize(memwr.data) == 0)
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continue;
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if (GetSize(memwr.address) == 0)
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memwr.address = State::S0;
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Const priority_mask;
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for (auto x : swizzle) {
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priority_mask.bits().push_back(memwr.priority_mask[x]);
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}
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memwr.priority_mask = priority_mask;
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swizzle.push_back(i);
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new_memwr_actions.push_back(memwr);
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}
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std::swap(new_memwr_actions, sync->mem_write_actions);
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std::vector<SigSig> new_actions;
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for (auto &action : sync->actions)
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if (GetSize(action.first) != 0)
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new_actions.push_back(action);
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std::swap(new_actions, sync->actions);
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}
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}
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for (auto &mem : Mem::get_selected_memories(module)) {
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if (mem.width == 0) {
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mem.remove();
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continue;
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}
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for (auto &init : mem.inits) {
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if (GetSize(init.addr) == 0) {
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init.addr = State::S0;
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}
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}
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for (auto &port : mem.rd_ports) {
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if (GetSize(port.addr) == 0) {
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port.addr = State::S0;
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}
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}
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for (auto &port : mem.wr_ports) {
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if (GetSize(port.addr) == 0) {
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port.addr = State::S0;
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}
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}
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mem.emit();
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}
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std::vector<SigSig> new_conns;
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for (auto &conn : module->connections())
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if (GetSize(conn.first) != 0)
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new_conns.push_back(conn);
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module->new_connections(new_conns);
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}
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}
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} CleanZeroWidthPass;
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PRIVATE_NAMESPACE_END
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