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18 lines
474 B
Verilog
18 lines
474 B
Verilog
// Whatever the initial content of this memory is at reset, it will never change
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// see demo3.smtc for assumptions and assertions
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module demo3(input clk, rst, input [15:0] addr, output reg [31:0] data);
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reg [31:0] mem [0:2**16-1];
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reg [15:0] addr_q;
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always @(posedge clk) begin
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if (rst) begin
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data <= mem[0] ^ 123456789;
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addr_q <= 0;
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end else begin
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mem[addr_q] <= data ^ 123456789;
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data <= mem[addr] ^ 123456789;
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addr_q <= addr;
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end
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end
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endmodule
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