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https://github.com/YosysHQ/yosys
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50d532f01c
Our techmap rules for $shift and $shiftx cells contained a special path that aimed to decompose the shift LSB-first instead of MSB-first in select cases that come up in pmux lowering. This path was needlessly overcomplicated and contained bugs. Instead of doing that, just switch over the main path to iterate LSB-first (except for the specially-handled MSB for signed shifts and overflow handling). This also makes the code consistent with shl/shr/sshl/sshr cells, which are already decomposed LSB-first. Fixes #2346.
110 lines
1.9 KiB
Plaintext
110 lines
1.9 KiB
Plaintext
read_verilog <<EOT
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module sc1 (i1 ,
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i2 ,
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i3 ,
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i4 ,
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i5 ,
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i6 ,
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i7 ,
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i8 ,
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i9 ,
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i10,
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i11,
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i12,
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i13,
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i14,
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i15,
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binary_out,
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encoder_in,
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enable
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);
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input [3:0] i1 ;
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input [3:0] i2 ;
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input [3:0] i3 ;
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input [3:0] i4 ;
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input [3:0] i5 ;
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input [3:0] i6 ;
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input [3:0] i7 ;
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input [3:0] i8 ;
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input [3:0] i9 ;
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input [3:0] i10 ;
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input [3:0] i11 ;
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input [3:0] i12 ;
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input [3:0] i13 ;
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input [3:0] i14 ;
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input [3:0] i15 ;
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output reg [3:0] binary_out ;
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input [3:0] encoder_in ;
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input enable ;
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always @ (*)
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begin
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binary_out = 0;
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if (enable) begin
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case (encoder_in)
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4'h1 : binary_out = i1;
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4'h2 : binary_out = i2;
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4'h3 : binary_out = i3;
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4'h4 : binary_out = i4;
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4'h5 : binary_out = i5;
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4'h6 : binary_out = i6;
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4'h7 : binary_out = i7;
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4'h8 : binary_out = i8;
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4'h9 : binary_out = i9;
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4'ha : binary_out = i10;
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4'hb : binary_out = i11;/*
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4'hc : binary_out = i12;
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4'hd : binary_out = i13;
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4'he : binary_out = i14;
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4'hf : binary_out = i15;*/
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endcase
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end
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end
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endmodule
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EOT
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proc
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pmux2shiftx
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design -save gold
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design -load gold
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techmap
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abc -lut 6
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select -assert-count 16 t:$lut
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -load gold
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techmap
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abc9 -lut 6
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select -assert-count 16 t:$lut
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design -stash gate
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design -import gold -as gold
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design -import gate -as gate
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -show-ports miter
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design -reset
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read_verilog <<EOT
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module top(input [6:0] A, input [1:0] B, output [1:0] Y);
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wire [7:0] AA = {1'bx, A};
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assign Y = AA[B*2 +: 2];
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endmodule
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EOT
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opt
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wreduce
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equiv_opt techmap
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