yosys/tests/various/sv_defines_dup.ys at a5960ce515847306d1fefdf174e1ec8c8be41761 - mirrors/yosys - Libre-Chip.org

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Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend

This patch should support things like

  `define foo(a, b = 3, c)   a+b+c

  `foo(1, ,2)

which will evaluate to 1+3+2. It also spots mistakes like

  `foo(1)

(the 3rd argument doesn't have a default value, so a call site is
required to set it).

Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.

Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.

Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.

2020-03-27 16:08:26 +00:00

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 # Check for duplicate arguments
 logger -expect error "Duplicate macro arguments with name `x'" 1
 read_verilog <<EOT
 `define duplicate_arg(x, x)
 EOT