mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
db5b76edc1
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
9 lines
199 B
Text
9 lines
199 B
Text
read_verilog << EOF
|
|
module uut_00034(b, y);
|
|
input signed [30:0] b;
|
|
output [11:0] y = b >> ~31'b0; // shift by INT_MAX
|
|
endmodule
|
|
EOF
|
|
|
|
# This should succeed, even with UBSAN halt_on_error
|
|
opt_expr
|