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	meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
		
			
				
	
	
		
			3 lines
		
	
	
	
		
			48 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			3 lines
		
	
	
	
		
			48 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| module a;
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| parameter integer real x=0;
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| endmodule
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