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37 lines
1.6 KiB
Text
37 lines
1.6 KiB
Text
# Check that blockram memory without parameters is not modified
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top block_ram
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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# Check that distributed memory without parameters is not modified
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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hierarchy -top distributed_ram
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synth_xilinx -top distributed_ram -noiopad
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cd distributed_ram # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAM32M
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# Set ram_style distributed to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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setattr -set ram_style "distributed" block_ram/m:*
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 16 t:RAM256X1S
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# Set synthesis, logic_block to blockram memory; will be implemented as distributed
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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setattr -set logic_block 1 block_ram/m:*
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synth_xilinx -top block_ram -noiopad
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cd block_ram # Constrain all select calls below inside the top module
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select -assert-count 0 t:RAMB18E1
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# Set ram_style block to a distributed memory; will be implemented as blockram
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design -reset
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read_verilog ../common/memory_attributes/attributes_test.v
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synth_xilinx -top distributed_ram_manual -noiopad
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cd distributed_ram_manual # Constrain all select calls below inside the top module
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select -assert-count 1 t:RAMB18E1
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