mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 19:52:31 +00:00 
			
		
		
		
	
		
			
				
	
	
		
			12 lines
		
	
	
	
		
			151 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			12 lines
		
	
	
	
		
			151 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| module top
 | |
| (
 | |
|     input [3:0] x,
 | |
|     input [3:0] y,
 | |
| 
 | |
|     output [3:0] A,
 | |
|     output [3:0] B
 | |
| );
 | |
| 
 | |
|     assign A =  x + y;
 | |
|     assign B =  x - y;
 | |
| endmodule
 |