yosys/tests/verilog/bug5160.v at a519390fc41ff07c3eba54386528b85c6be5a4f6 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-07-20 11:22:05 +00:00

garytwong a519390fc4 verilog: fix string literal regular expression (#5187 )

* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).

2025-07-10 23:16:50 +02:00

5 lines

169 B

Verilog

Raw Blame History

 // Regression test for bug mentioned in #5160:
 // https://github.com/YosysHQ/yosys/pull/5160#issuecomment-2983643084
 module top;
     initial $display( "\\" );
 endmodule