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yosys/backends
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Eddie Hung 14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
2019-08-20 11:59:31 -07:00
..
aiger Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 2019-08-20 11:59:31 -07:00
blif RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
btor Use State::S{0,1} 2019-08-06 16:22:47 -07:00
edif Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
firrtl Merge pull request #1258 from YosysHQ/eddie/cleanup 2019-08-10 09:52:14 +02:00
ilang RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
intersynth substr() -> compare() 2019-08-07 12:20:08 -07:00
json Implement improved JSON attr/param encoding 2019-08-01 12:34:52 +02:00
protobuf Support filename rewrite in backends 2019-06-18 14:39:52 -07:00
simplec Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 2019-08-06 04:47:55 +02:00
smt2 substr() -> compare() 2019-08-07 12:20:08 -07:00
smv substr() -> compare() 2019-08-07 12:20:08 -07:00
spice Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog substr() -> compare() 2019-08-07 12:20:08 -07:00