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27 lines
584 B
Systemverilog
27 lines
584 B
Systemverilog
module top;
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reg [0:7] mem [0:2];
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initial mem[1] = '1;
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wire [31:0] a, b, c, d;
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assign a = mem[1];
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assign b = mem[-1];
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assign c = mem[-1][0];
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assign d = mem[-1][0:1];
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always @* begin
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assert ($countbits(a, '0) == 24);
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assert ($countbits(a, '1) == 8);
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assert ($countbits(a, 'x) == 0);
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assert ($countbits(b, '0) == 24);
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assert ($countbits(b, 'x) == 8);
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assert ($countbits(c, '0) == 31);
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assert ($countbits(c, 'x) == 1);
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assert ($countbits(d, '0) == 30);
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assert ($countbits(d, 'x) == 2);
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end
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endmodule
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