mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-03 21:09:12 +00:00
aa35f24290
If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
16 lines
233 B
Text
16 lines
233 B
Text
read_verilog -sv <<EOF
|
|
module top;
|
|
logic [4:0] x;
|
|
logic z;
|
|
assign z = 1'b1;
|
|
always_comb begin
|
|
x = '0;
|
|
if (z) begin
|
|
for (int i = 0; i < 5; i++) begin
|
|
x[i] = 1'b1;
|
|
end
|
|
end
|
|
end
|
|
endmodule
|
|
EOF
|
|
proc
|