yosys/tests/verilog/absurd_width.ys at a4dc0156bb027de90719305ab674dc3c5e5f7bbb - mirrors/yosys - Libre-Chip.org

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Zachary Snow c18ddbcd82 verilog: impose limit on maximum expression width

Designs with unreasonably wide expressions would previously get stuck
allocating memory forever.

2021-03-04 15:20:52 -05:00

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 logger -expect error "Expression width 1073741824 exceeds implementation limit of 16777216!" 1
 read_verilog <<EOF
 module top(
     input inp,
     output out
 );
     assign out =
         {1024 {
         {1024 {
         {1024 {
         inp
         }}
         }}
         }}
         ;
 endmodule
 EOF