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29 lines
394 B
Verilog
29 lines
394 B
Verilog
module tb;
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reg clk, rst;
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wire [7:0] out;
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wire [4:0] counter;
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uut uut (clk, rst, out, counter);
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initial begin
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#5 clk <= 0;
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repeat (100) #5 clk <= ~clk;
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#5 $finish;
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end
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initial begin
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rst <= 1;
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repeat (2) @(posedge clk);
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rst <= 0;
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end
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always @(posedge clk)
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$display("%d %d %d", rst, out, counter);
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initial begin
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$dumpfile("mem_simple_4x1_tb.vcd");
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$dumpvars(0, uut);
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end
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endmodule
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