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https://github.com/YosysHQ/yosys
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52 lines
1.5 KiB
Text
52 lines
1.5 KiB
Text
read_verilog <<EOT
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module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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assign gtu = a > b;
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assign gts = $signed(a) > $signed(b);
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assign ltu = a < b;
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assign lts = $signed(a) < $signed(b);
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assign geu = a >= b;
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assign ges = $signed(a) >= $signed(b);
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assign leu = a <= b;
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assign les = $signed(a) <= $signed(b);
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endmodule
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EOT
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=5 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -load preopt
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=7 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -reset
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read_verilog <<EOT
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module top(input [8:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les);
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wire [13:0] c = {a[8:6], 3'b101, a[5:4], 2'b11, a[3:0]};
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wire [13:0] d = {b[8], 3'b101, b[7:4], 2'b01, b[3:0]};
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assign gtu = c > d;
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assign gts = $signed(c) > $signed(d);
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assign ltu = c < d;
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assign lts = $signed(c) < $signed(d);
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assign geu = c >= d;
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assign ges = $signed(c) >= $signed(d);
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assign leu = c <= d;
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assign les = $signed(c) <= $signed(d);
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endmodule
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EOT
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design -save gold
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=5
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=2 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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design -load preopt
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equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=3
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design -load postopt
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select -assert-count 8 t:$lcu r:WIDTH=4 %i
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select -assert-none t:$gt t:$ge t:$lt t:$le
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