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13 lines
241 B
Text
13 lines
241 B
Text
read_verilog -icells <<EOF
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module top(input wire [2:0] a, output wire [2:0] y);
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\$buf #(.WIDTH(3)) b(.A(a), .Y(y));
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endmodule
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EOF
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design -save save
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opt_clean
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select -assert-none t:$buf
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design -load save
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techmap
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select -assert-none t:$buf
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