mirror of
https://github.com/YosysHQ/yosys
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148 lines
3 KiB
Text
148 lines
3 KiB
Text
log -header "Test simple positive case"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input signed [7:0] a,
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input signed [7:0] b,
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output signed [8:0] result
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);
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assign result = - (a - b);
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-none t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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log -header "Test positive case with intermediate signal"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input signed [7:0] a,
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input signed [7:0] b,
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output signed [8:0] result
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);
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wire signed [8:0] difference;
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assign difference = a - b;
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assign result = - difference;
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-none t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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log -header "Test negative case (fanout)"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input signed [7:0] a,
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input signed [7:0] b,
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output signed [8:0] result,
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output signed [8:0] not_diff
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);
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wire signed [8:0] difference;
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assign difference = a - b;
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assign result = -difference;
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assign not_diff = ~difference;
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-any t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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log -header "Test negative case (unsigned intermediate signal)"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input signed [7:0] a,
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input signed [7:0] b,
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output signed [8:0] result
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);
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wire [8:0] difference;
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assign difference = a - b;
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assign result = -difference;
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-any t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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log -header "Test negative case, inputs are not signed"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input [7:0] a,
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input [7:0] b,
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output signed [8:0] result
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);
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assign result = - (a - b);
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-any t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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log -header "Negative case with disconnected intermediate signal (operator in the middle)"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input signed [7:0] a,
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input signed [7:0] b,
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output signed [8:0] result
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);
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wire signed [8:0] difference;
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wire signed [8:0] c;
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assign difference = a - b;
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assign c = ~difference;
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assign result = - c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-any t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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log -header "Negative case with disconnected intermediate signal"
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log -push
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design -reset
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read_verilog <<EOF
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module equation_example (
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input signed [7:0] a,
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input signed [7:0] b,
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output signed [8:0] result
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);
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wire signed [8:0] difference;
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wire signed [8:0] c;
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assign difference = a - b;
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assign c = a + b ;
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assign result = - c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert -post peepopt
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select -assert-any t:$neg
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select -assert-any t:$sub
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design -reset
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log -pop
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