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yosys/passes
History
George Rennie 8f6058a7d6 bufnorm: preserve constant bits driving wires
2024-11-07 11:48:48 +01:00
..
cmds Merge pull request #4707 from povik/stat-unused 2024-11-05 09:38:29 +01:00
equiv equiv_simple: Take FFs into account for driver map 2024-02-21 12:05:52 +01:00
fsm rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
hierarchy rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
memory rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
opt rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
pmgen rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
proc rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
sat rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
techmap bufnorm: preserve constant bits driving wires 2024-11-07 11:48:48 +01:00
tests rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00