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tests
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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abc9_model.v
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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arith_map.v
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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brams_defs.vh
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc2v.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc2v_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc3sda.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc3sda_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc4v.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc4v_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc5v_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xc6v_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xcu_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xcv.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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brams_xcv_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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cells_map.v
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iopadmap: Add native support for negative-polarity output enable.
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2021-11-09 15:40:16 +01:00 |
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cells_sim.v
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Check DREG attribute
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2023-02-17 17:54:41 +01:00 |
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cells_xtra.py
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xilinx: Add RAMB4* blackboxes
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2022-03-21 13:11:52 +01:00 |
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cells_xtra.v
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xilinx: Add RAMB4* blackboxes
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2022-03-21 13:11:52 +01:00 |
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ff_map.v
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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lut_map.v
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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lutrams_xc5v.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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lutrams_xc5v_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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lutrams_xcu.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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lutrams_xcv.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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lutrams_xcv_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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Makefile.inc
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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mux_map.v
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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synth_xilinx.cc
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Fitting help messages to 80 character width
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2022-08-24 10:40:57 +12:00 |
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urams.txt
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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urams_map.v
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xilinx: Use memory_libmap pass.
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2022-05-18 17:32:56 +02:00 |
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xc3s_mult_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc3sda_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc4v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc5v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc6s_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc7_dsp_map.v
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xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
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2020-09-23 09:15:24 -07:00 |
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xcu_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xilinx_dffopt.cc
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Fixing old e-mail addresses and deadnames
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2021-06-08 00:39:36 +02:00 |
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