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https://github.com/YosysHQ/yosys
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82 lines
2.2 KiB
Verilog
82 lines
2.2 KiB
Verilog
module switch_fabric(
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clk, reset, data_in0, data_in1, data_in2,
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data_in3, data_in4, data_in5, data_in_valid0,
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data_in_valid1, data_in_valid2, data_in_valid3,
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data_in_valid4, data_in_valid5, data_out0,
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data_out1, data_out2, data_out3, data_out4,
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data_out5, data_out_ack0, data_out_ack1,
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data_out_ack2, data_out_ack3, data_out_ack4,
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data_out_ack5
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);
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input clk, reset;
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input [7:0] data_in0, data_in1, data_in2, data_in3;
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input [7:0] data_in4, data_in5;
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input data_in_valid0, data_in_valid1, data_in_valid2;
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input [7:0] data_in_valid3, data_in_valid4, data_in_valid5;
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output [7:0] data_out0, data_out1, data_out2, data_out3;
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output [7:0] data_out4, data_out5;
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output data_out_ack0, data_out_ack1, data_out_ack2;
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output [7:0] data_out_ack3, data_out_ack4, data_out_ack5;
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(* gentb_clock *)
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wire clk;
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switch port_0 ( .clk(clk), .reset(reset), .data_in(data_in0),
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.data_in_valid(data_in_valid0), .data_out(data_out0),
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.data_out_ack(data_out_ack0));
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switch port_1 ( .clk(clk), .reset(reset), .data_in(data_in1),
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.data_in_valid(data_in_valid1), .data_out(data_out1),
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.data_out_ack(data_out_ack1));
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switch port_2 ( .clk(clk), .reset(reset), .data_in(data_in2),
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.data_in_valid(data_in_valid2), .data_out(data_out2), .
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data_out_ack(data_out_ack2));
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switch port_3 ( .clk(clk), .reset(reset), .data_in(data_in3),
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.data_in_valid(data_in_valid3), .data_out(data_out3),
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.data_out_ack(data_out_ack3));
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switch port_4 ( .clk(clk), .reset(reset), .data_in(data_in4),
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.data_in_valid(data_in_valid4), .data_out(data_out4),
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.data_out_ack(data_out_ack4));
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switch port_5 ( .clk(clk), .reset(reset), .data_in(data_in5),
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.data_in_valid(data_in_valid5), .data_out(data_out5),
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.data_out_ack(data_out_ack5));
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endmodule
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module switch (
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clk,
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reset,
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data_in,
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data_in_valid,
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data_out,
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data_out_ack
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);
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input clk;
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input reset;
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input [7:0] data_in;
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input data_in_valid;
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output [7:0] data_out;
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output data_out_ack;
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reg [7:0] data_out;
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reg data_out_ack;
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always @ (posedge clk)
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if (reset) begin
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data_out <= 0;
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data_out_ack <= 0;
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end else if (data_in_valid) begin
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data_out <= data_in;
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data_out_ack <= 1;
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end else begin
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data_out <= 0;
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data_out_ack <= 0;
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end
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endmodule
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