mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 19:52:31 +00:00
349 lines
7.9 KiB
Verilog
349 lines
7.9 KiB
Verilog
module $__DP8KC_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_A_WIDTH = 18;
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parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
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input PORT_A_CLK;
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input PORT_A_CLK_EN;
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input PORT_A_WR_EN;
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input PORT_A_RD_SRST;
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input PORT_A_RD_ARST;
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input [12:0] PORT_A_ADDR;
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input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
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output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
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parameter PORT_B_WIDTH = 18;
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parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
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input PORT_B_CLK;
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input PORT_B_CLK_EN;
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input PORT_B_WR_EN;
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input PORT_B_RD_SRST;
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input PORT_B_RD_ARST;
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input [12:0] PORT_B_ADDR;
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input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
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output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
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function [319:0] init_slice;
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input integer idx;
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integer i, j;
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init_slice = 0;
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for (i = 0; i < 16; i = i + 1) begin
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init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
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end
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endfunction
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wire [8:0] DOA;
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wire [8:0] DOB;
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wire [8:0] DIA;
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wire [8:0] DIB;
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case(PORT_A_WIDTH)
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1: assign DIA = {7'bx, PORT_A_WR_DATA[0], 1'bx};
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2: assign DIA = {3'bx, PORT_A_WR_DATA[1], 2'bx, PORT_A_WR_DATA[0], 2'bx};
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default: assign DIA = PORT_A_WR_DATA;
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endcase
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case(PORT_B_WIDTH)
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1: assign DIB = {7'bx, PORT_B_WR_DATA[0], 1'bx};
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2: assign DIB = {3'bx, PORT_B_WR_DATA[1], 2'bx, PORT_B_WR_DATA[0], 2'bx};
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default: assign DIB = PORT_B_WR_DATA;
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endcase
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assign PORT_A_RD_DATA = DOA;
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assign PORT_B_RD_DATA = DOB;
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DP8KC #(
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.INITVAL_00(init_slice('h00)),
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.INITVAL_01(init_slice('h01)),
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.INITVAL_02(init_slice('h02)),
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.INITVAL_03(init_slice('h03)),
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.INITVAL_04(init_slice('h04)),
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.INITVAL_05(init_slice('h05)),
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.INITVAL_06(init_slice('h06)),
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.INITVAL_07(init_slice('h07)),
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.INITVAL_08(init_slice('h08)),
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.INITVAL_09(init_slice('h09)),
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.INITVAL_0A(init_slice('h0a)),
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.INITVAL_0B(init_slice('h0b)),
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.INITVAL_0C(init_slice('h0c)),
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.INITVAL_0D(init_slice('h0d)),
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.INITVAL_0E(init_slice('h0e)),
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.INITVAL_0F(init_slice('h0f)),
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.INITVAL_10(init_slice('h10)),
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.INITVAL_11(init_slice('h11)),
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.INITVAL_12(init_slice('h12)),
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.INITVAL_13(init_slice('h13)),
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.INITVAL_14(init_slice('h14)),
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.INITVAL_15(init_slice('h15)),
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.INITVAL_16(init_slice('h16)),
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.INITVAL_17(init_slice('h17)),
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.INITVAL_18(init_slice('h18)),
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.INITVAL_19(init_slice('h19)),
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.INITVAL_1A(init_slice('h1a)),
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.INITVAL_1B(init_slice('h1b)),
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.INITVAL_1C(init_slice('h1c)),
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.INITVAL_1D(init_slice('h1d)),
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.INITVAL_1E(init_slice('h1e)),
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.INITVAL_1F(init_slice('h1f)),
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.DATA_WIDTH_A(PORT_A_WIDTH),
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.DATA_WIDTH_B(PORT_B_WIDTH),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.RESETMODE(OPTION_RESETMODE),
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.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
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.CSDECODE_A("0b000"),
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.CSDECODE_B("0b000"),
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.WRITEMODE_A(PORT_A_OPTION_WRITEMODE),
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.WRITEMODE_B(PORT_B_OPTION_WRITEMODE),
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.GSR("AUTO")
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) _TECHMAP_REPLACE_ (
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.CLKA(PORT_A_CLK),
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.WEA(PORT_A_WR_EN),
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.CEA(PORT_A_CLK_EN),
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.OCEA(1'b1),
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.RSTA(OPTION_RESETMODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST),
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.CSA0(1'b0),
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.CSA1(1'b0),
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.CSA2(1'b0),
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.ADA0(PORT_A_WIDTH == 9 ? 1'b1 : PORT_A_ADDR[0]),
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.ADA1(PORT_A_ADDR[1]),
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.ADA2(PORT_A_ADDR[2]),
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.ADA3(PORT_A_ADDR[3]),
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.ADA4(PORT_A_ADDR[4]),
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.ADA5(PORT_A_ADDR[5]),
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.ADA6(PORT_A_ADDR[6]),
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.ADA7(PORT_A_ADDR[7]),
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.ADA8(PORT_A_ADDR[8]),
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.ADA9(PORT_A_ADDR[9]),
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.ADA10(PORT_A_ADDR[10]),
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.ADA11(PORT_A_ADDR[11]),
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.ADA12(PORT_A_ADDR[12]),
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.DIA0(DIA[0]),
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.DIA1(DIA[1]),
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.DIA2(DIA[2]),
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.DIA3(DIA[3]),
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.DIA4(DIA[4]),
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.DIA5(DIA[5]),
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.DIA6(DIA[6]),
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.DIA7(DIA[7]),
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.DIA8(DIA[8]),
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.DOA0(DOA[0]),
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.DOA1(DOA[1]),
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.DOA2(DOA[2]),
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.DOA3(DOA[3]),
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.DOA4(DOA[4]),
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.DOA5(DOA[5]),
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.DOA6(DOA[6]),
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.DOA7(DOA[7]),
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.DOA8(DOA[8]),
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.CLKB(PORT_B_CLK),
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.WEB(PORT_B_WR_EN),
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.CEB(PORT_B_CLK_EN),
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.OCEB(1'b1),
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.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST),
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.CSB0(1'b0),
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.CSB1(1'b0),
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.CSB2(1'b0),
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.ADB0(PORT_B_WIDTH == 9 ? 1'b1 : PORT_B_ADDR[0]),
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.ADB1(PORT_B_ADDR[1]),
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.ADB2(PORT_B_ADDR[2]),
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.ADB3(PORT_B_ADDR[3]),
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.ADB4(PORT_B_ADDR[4]),
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.ADB5(PORT_B_ADDR[5]),
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.ADB6(PORT_B_ADDR[6]),
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.ADB7(PORT_B_ADDR[7]),
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.ADB8(PORT_B_ADDR[8]),
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.ADB9(PORT_B_ADDR[9]),
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.ADB10(PORT_B_ADDR[10]),
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.ADB11(PORT_B_ADDR[11]),
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.ADB12(PORT_B_ADDR[12]),
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.DIB0(DIB[0]),
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.DIB1(DIB[1]),
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.DIB2(DIB[2]),
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.DIB3(DIB[3]),
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.DIB4(DIB[4]),
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.DIB5(DIB[5]),
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.DIB6(DIB[6]),
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.DIB7(DIB[7]),
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.DIB8(DIB[8]),
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.DOB0(DOB[0]),
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.DOB1(DOB[1]),
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.DOB2(DOB[2]),
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.DOB3(DOB[3]),
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.DOB4(DOB[4]),
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.DOB5(DOB[5]),
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.DOB6(DOB[6]),
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.DOB7(DOB[7]),
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.DOB8(DOB[8]),
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);
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endmodule
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module $__PDPW8KC_ (...);
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parameter INIT = 0;
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parameter OPTION_RESETMODE = "SYNC";
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parameter PORT_R_WIDTH = 18;
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input PORT_R_CLK;
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input PORT_R_CLK_EN;
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input PORT_R_RD_SRST;
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input PORT_R_RD_ARST;
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input [12:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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parameter PORT_W_WIDTH = 18;
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parameter PORT_W_WR_EN_WIDTH = 2;
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input PORT_W_CLK;
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input PORT_W_CLK_EN;
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input [12:0] PORT_W_ADDR;
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input [PORT_W_WR_EN_WIDTH-1:0] PORT_W_WR_EN;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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function [319:0] init_slice;
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input integer idx;
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integer i, j;
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init_slice = 0;
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for (i = 0; i < 16; i = i + 1) begin
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init_slice[i*20+:18] = INIT[(idx * 16 + i) * 18+:18];
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end
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endfunction
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wire [17:0] DI = PORT_W_WR_DATA;
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wire [17:0] DO;
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assign PORT_R_RD_DATA = PORT_R_WIDTH == 18 ? DO : DO[17:9];
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DP8KC #(
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.INITVAL_00(init_slice('h00)),
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.INITVAL_01(init_slice('h01)),
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.INITVAL_02(init_slice('h02)),
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.INITVAL_03(init_slice('h03)),
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.INITVAL_04(init_slice('h04)),
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.INITVAL_05(init_slice('h05)),
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.INITVAL_06(init_slice('h06)),
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.INITVAL_07(init_slice('h07)),
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.INITVAL_08(init_slice('h08)),
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.INITVAL_09(init_slice('h09)),
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.INITVAL_0A(init_slice('h0a)),
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.INITVAL_0B(init_slice('h0b)),
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.INITVAL_0C(init_slice('h0c)),
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.INITVAL_0D(init_slice('h0d)),
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.INITVAL_0E(init_slice('h0e)),
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.INITVAL_0F(init_slice('h0f)),
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.INITVAL_10(init_slice('h10)),
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.INITVAL_11(init_slice('h11)),
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.INITVAL_12(init_slice('h12)),
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.INITVAL_13(init_slice('h13)),
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.INITVAL_14(init_slice('h14)),
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.INITVAL_15(init_slice('h15)),
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.INITVAL_16(init_slice('h16)),
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.INITVAL_17(init_slice('h17)),
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.INITVAL_18(init_slice('h18)),
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.INITVAL_19(init_slice('h19)),
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.INITVAL_1A(init_slice('h1a)),
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.INITVAL_1B(init_slice('h1b)),
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.INITVAL_1C(init_slice('h1c)),
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.INITVAL_1D(init_slice('h1d)),
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.INITVAL_1E(init_slice('h1e)),
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.INITVAL_1F(init_slice('h1f)),
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.DATA_WIDTH_A(PORT_W_WIDTH),
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.DATA_WIDTH_B(PORT_R_WIDTH),
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.REGMODE_A("NOREG"),
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.REGMODE_B("NOREG"),
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.RESETMODE(OPTION_RESETMODE),
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.ASYNC_RESET_RELEASE(OPTION_RESETMODE),
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.CSDECODE_A("0b000"),
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.CSDECODE_B("0b000"),
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.GSR("AUTO")
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) _TECHMAP_REPLACE_ (
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.CLKA(PORT_W_CLK),
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.WEA(PORT_W_WIDTH >= 9 ? 1'b1 : PORT_W_WR_EN[0]),
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.CEA(PORT_W_CLK_EN),
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.OCEA(1'b0),
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.RSTA(1'b0),
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.CSA0(1'b0),
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.CSA1(1'b0),
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.CSA2(1'b0),
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.ADA0(PORT_W_WIDTH >= 9 ? PORT_W_WR_EN[0] : PORT_W_ADDR[0]),
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.ADA1(PORT_W_WIDTH >= 18 ? PORT_W_WR_EN[1] : PORT_W_ADDR[1]),
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.ADA2(PORT_W_ADDR[2]),
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.ADA3(PORT_W_ADDR[3]),
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.ADA4(PORT_W_ADDR[4]),
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.ADA5(PORT_W_ADDR[5]),
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.ADA6(PORT_W_ADDR[6]),
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.ADA7(PORT_W_ADDR[7]),
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.ADA8(PORT_W_ADDR[8]),
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.ADA9(PORT_W_ADDR[9]),
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.ADA10(PORT_W_ADDR[10]),
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.ADA11(PORT_W_ADDR[11]),
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.ADA12(PORT_W_ADDR[12]),
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.DIA0(DI[0]),
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.DIA1(DI[1]),
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.DIA2(DI[2]),
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.DIA3(DI[3]),
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.DIA4(DI[4]),
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.DIA5(DI[5]),
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.DIA6(DI[6]),
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.DIA7(DI[7]),
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.DIA8(DI[8]),
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.DIB0(DI[9]),
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.DIB1(DI[10]),
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.DIB2(DI[11]),
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.DIB3(DI[12]),
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.DIB4(DI[13]),
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.DIB5(DI[14]),
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.DIB6(DI[15]),
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.DIB7(DI[16]),
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.DIB8(DI[17]),
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.CLKB(PORT_R_CLK),
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.WEB(1'b0),
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.CEB(PORT_R_CLK_EN),
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.OCEB(1'b1),
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.RSTB(OPTION_RESETMODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST),
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.CSB0(1'b0),
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.CSB1(1'b0),
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.CSB2(1'b0),
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.ADB0(PORT_R_ADDR[0]),
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.ADB1(PORT_R_ADDR[1]),
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.ADB2(PORT_R_ADDR[2]),
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.ADB3(PORT_R_ADDR[3]),
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.ADB4(PORT_R_ADDR[4]),
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.ADB5(PORT_R_ADDR[5]),
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.ADB6(PORT_R_ADDR[6]),
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.ADB7(PORT_R_ADDR[7]),
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.ADB8(PORT_R_ADDR[8]),
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.ADB9(PORT_R_ADDR[9]),
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.ADB10(PORT_R_ADDR[10]),
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.ADB11(PORT_R_ADDR[11]),
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.ADB12(PORT_R_ADDR[12]),
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.DOA0(DO[0]),
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.DOA1(DO[1]),
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.DOA2(DO[2]),
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.DOA3(DO[3]),
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.DOA4(DO[4]),
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.DOA5(DO[5]),
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.DOA6(DO[6]),
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.DOA7(DO[7]),
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.DOA8(DO[8]),
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.DOB0(DO[9]),
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.DOB1(DO[10]),
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.DOB2(DO[11]),
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.DOB3(DO[12]),
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.DOB4(DO[13]),
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.DOB5(DO[14]),
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.DOB6(DO[15]),
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.DOB7(DO[16]),
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.DOB8(DO[17]),
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);
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endmodule
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