mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 11:42:30 +00:00 
			
		
		
		
	
		
			
				
	
	
		
			4 lines
		
	
	
	
		
			66 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
			
		
		
	
	
			4 lines
		
	
	
	
		
			66 B
		
	
	
	
		
			Verilog
		
	
	
	
	
	
| module sub;
 | |
|     sub _TECHMAP_REPLACE_ ();
 | |
|     bar f0();
 | |
| endmodule
 |