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yosys/frontends
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Marcelina Kościelnicka 52cbf1bea5 verilog: Support tri/triand/trior wire types. 
These are, by the standard, just aliases for wire/wand/wor.

Fixes #2918.
2021-08-06 21:35:43 +02:00
..
aiger Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ast genrtlil: add width detection for AST_PREFIX nodes 2021-07-29 20:55:31 -04:00
blif Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
json Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
liberty Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: Make Process handling more uniform with Cell and Wire. 2021-07-12 00:47:34 +02:00
verific Require latest verific 2021-08-02 10:29:58 +02:00
verilog verilog: Support tri/triand/trior wire types. 2021-08-06 21:35:43 +02:00