Eddie Hung e18aeda7ed Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards ... Just like Verilog...		2020-01-27 14:02:13 -08:00
..
tests
.gitignore
abc9_hx.box
abc9_hx.lut
abc9_lp.box
abc9_lp.lut
abc9_model.v
abc9_u.box
abc9_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v
dsp_map.v
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards	2020-01-27 14:02:13 -08:00
latches_map.v
Makefile.inc
synth_ice40.cc