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Code Activity
yosys/passes
History
Emil J. Tywoniak a1d13b821e rtlil: set Module::design before name at all construction sites
2026-07-20 12:26:39 +02:00
..
cmds rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-07-20 12:26:39 +02:00
equiv WIP 2026-07-17 23:48:54 +02:00
fsm WIP 2026-07-17 23:48:54 +02:00
hierarchy rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
memory rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-07-20 12:26:39 +02:00
opt twine 2026-07-20 12:26:39 +02:00
pmgen pmgen: hold sigmap pointer instead of owning it 2026-07-17 23:38:01 +02:00
proc rtlil: set Module* on inner-process AttrObjects at construction 2026-07-20 12:26:39 +02:00
sat rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
techmap rtlil: set Module::design before name at all construction sites 2026-07-20 12:26:39 +02:00
tests End of file fix 2026-06-23 07:23:41 +02:00
CMakeLists.txt Migrate build system to CMake 2026-06-03 08:58:10 +00:00