Ben Widawsky 8767ec3fbd Add a few more filename rewrites ... This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net>		2019-06-20 10:27:59 -07:00
..
assertpmux.cc	Fixed the help summary line for a few commands	2019-06-19 15:27:04 -04:00
async2sync.cc	Add $dffsr support to async2sync	2019-03-09 11:52:00 -08:00
clk2fflogic.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
cutpoint.cc	Fixed the help summary line for a few commands	2019-06-19 15:27:04 -04:00
eval.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
example.v	Added support for shifter cells to SAT generator	2013-06-08 15:12:08 +02:00
example.ys	Fixes in old SAT example.ys	2014-09-01 11:45:47 +02:00
expose.cc	Update from master	2019-05-28 09:35:45 -07:00
fmcombine.cc	Fix typo in fmcombine log message, fixes #1063	2019-06-05 09:26:44 +02:00
freduce.cc	Consistent use of 'override' for virtual methods in derived classes.	2018-07-20 23:51:06 -07:00
Makefile.inc	Add "cutpoint" pass	2019-03-25 19:49:00 +01:00
miter.cc	Add "techmap -wb", use in formal flows	2019-04-20 11:23:24 +02:00
mutate.cc	Added missing argument checking to "mutate" command	2019-04-04 18:10:10 +02:00
sat.cc	Add a few more filename rewrites	2019-06-20 10:27:59 -07:00
sim.cc	Error out if no top module given before 'sim'	2019-06-05 14:16:24 -07:00
supercover.cc	Improvements in "supercover" pass	2019-02-27 11:45:13 -08:00