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yosys/tests/liberty/dff.lib.verilogsim.ok

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module dff (D, CLK, Q);
reg IQ, IQN;
input D;
input CLK;
output Q;
assign Q = IQ; // IQ
always @(posedge CLK) begin
// "(D)"
IQ <= D;
IQN <= ~(D);
end
endmodule