|
abc9_model.v
|
Create synth_analogdevices
|
2025-10-16 08:43:08 +01:00 |
|
arith_map.v
|
analogdevices: update timing model
|
2025-10-16 08:43:08 +01:00 |
|
brams.txt
|
analogdevices: Adding RBRAM2 and -tech
|
2025-10-16 08:43:08 +01:00 |
|
brams_defs.vh
|
Create synth_analogdevices
|
2025-10-16 08:43:08 +01:00 |
|
brams_map.v
|
analogdevices: Adding RBRAM2 and -tech
|
2025-10-16 08:43:08 +01:00 |
|
cells_map.v
|
Create synth_analogdevices
|
2025-10-16 08:43:08 +01:00 |
|
cells_sim.v
|
analogdevices: DSP tweaks
|
2025-10-18 12:10:50 +01:00 |
|
dsp_map.v
|
analogdevices: DSP inference
|
2025-10-16 23:33:59 +01:00 |
|
ff_map.v
|
test suite
|
2025-10-16 08:43:08 +01:00 |
|
lut_map.v
|
analogdevices: use single tech param
|
2025-10-16 08:43:08 +01:00 |
|
lutrams.txt
|
analogdevices: LUT RAM only on positive edge
|
2025-10-18 12:11:18 +01:00 |
|
lutrams_map.v
|
analogdevices: Native LUTRAM primitives
|
2025-10-16 08:43:08 +01:00 |
|
Makefile.inc
|
analogdevices: remove cells_xtra
|
2025-10-16 09:27:15 +01:00 |
|
mux_map.v
|
Create synth_analogdevices
|
2025-10-16 08:43:08 +01:00 |
|
retarget_map.v
|
analogdevices: user retargeting
|
2025-10-16 08:43:08 +01:00 |
|
synth_analogdevices.cc
|
analogdevices: DSP tweaks
|
2025-10-18 12:10:50 +01:00 |
