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Code Activity
yosys/techlibs/ecp5
History
Eddie Hung a270af00cc Put abc_* attributes above port
2019-08-23 11:21:44 -07:00
..
.gitignore
abc_5g.box Fix DO4 typo 2019-06-28 09:45:40 -07:00
abc_5g.lut ecp5: Add abc9 option 2019-06-14 17:15:02 +01:00
abc_5g_nowide.lut Add _nowide variants of LUT libraries in -nowidelut flows 2019-06-26 10:23:29 -07:00
arith_map.v ecp5: Improve mapping of $alu when BI is used 2019-06-21 09:45:11 +01:00
bram.txt
brams_connect.py
brams_init.py
brams_map.v
cells_bb.v ecp5: Add DDRDLLA 2019-02-19 19:34:37 +00:00
cells_map.v Merge origin/master 2019-06-27 11:20:15 -07:00
cells_sim.v Put abc_* attributes above port 2019-08-23 11:21:44 -07:00
ecp5_ffinit.cc ecp5: Demote conflicting FF init values to a warning 2019-03-04 11:26:20 +00:00
latches_map.v
lutram.txt synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
lutrams_map.v synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
Makefile.inc synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00
synth_ecp5.cc synth_ecp5: rename dram to lutram everywhere. 2019-07-16 20:45:12 +00:00