Akash Levy bc3ca6210c Add back operator optimization for Verific frontend		2025-03-17 04:06:28 -07:00
..
aiger
aiger2
ast	ast/dpicall: Stop using variable length array	2025-02-24 17:32:30 +01:00
blif	Resolve reg naming to some extent	2024-12-17 12:11:39 -08:00
json
liberty	Merge upstream	2025-03-05 07:54:26 -08:00
rpc
rtlil
verific	Add back operator optimization for Verific frontend	2025-03-17 04:06:28 -07:00
verilog	Address comments	2025-03-11 18:50:44 -04:00